1. Field of the Invention
The present invention relates to a layout device and a layout method of a semiconductor integrated circuit, and especially relates to a layout device and a layout method for crowded wiring of a semiconductor integrated circuit.
2. Description of the Related Art
In accordance with recent advancement of a microfabrication technique, high integration of an LSI is increasingly advanced. In addition, further faster operation is required. In a layout design of the LSI, it is known to carry out routing by using an automatic routing tool. In order to satisfy a timing of the high speed operation, the automatic routing tool carries out the shortest routing. However, volume of the wiring line included in one chip is increased due to the high integration of the LSI. Accordingly, there is a region such as a corner of a hard macro where there are many wiring lines whose routing paths are blocked and which are required to be bypassed and there is a region where wiring lines are crowed such as a wiring region where a high-speed signal exchange between a plurality of modules intersects. In the region where the wiring lines are crowded, following problems become increasingly prominent. One problem is a routing error caused because routing cannot be performed in a routing track completely (for example, short-circuiting or opening of a wiring line, a design rule violation and the like). The other problem is a timing problem that timing deteriorates because a wiring line is bypassed in order to avoid the routing error.
As a technique for preventing the deterioration of the timing caused by bypass routing, JP2008-227198A (Patent literature 1) discloses a layout design method of a semiconductor integrated circuit. The layout design method includes: a step of extracting a wiring crowding region from a required routing region and from an actually routing allowable region after performing placement of circuit elements constituting the semiconductor integrated circuit; a step of generating a routing prohibition region to the wiring crowding region; a step of carrying out an automatic routing while bypassing the wiring crowding region; and a step of carrying out the automatic routing again after deleting the routing prohibition region. That is, in order to avoid locally crowded wiring, a routing resource is preliminarily reserved at first by using the routing prohibition region. Then, in the initial routing, the automatic routing is carried out while the routing prohibition region is bypassed. Upon rerouting, the automatic routing is carried out after the routing prohibition region is deleted to release the routing resource.
The inventors have now discovered the following facts. A technique disclosed in JP2008-227198A has a problem that the number of routing errors increases after the automatic routing is carried out while the routing prohibition region is bypassed. For this reason, even when the automatic routing is carried out again after the routing prohibition region is deleted, there will be a problem that the number of the remaining routing errors that could not be corrected completely increases in proportion to increase of the routing error and additionally correction time of the routing error increases. A reason that the above-mentioned problem occurs will be described below.
As described above, the technique disclosed in JP2008-227198A firstly arranges circuit elements, carries out wiring estimation, specifies a region where wiring lines are crowded, and extracts coordinates covering the wiring crowding region. Then, the technique obtains an extension value by calculating the number of wiring lines that run short in the wiring crowding region, and generates the routing prohibition region by adding the obtained extension value to the coordinates covering the extracted wiring crowding region. Subsequently, the technique carries out the automatic routing so as to bypass the routing prohibition region. After that, the technique deletes the routing prohibition region, and carries out the rerouting to the reserved routing resource, preferentially applying a wiring line that requires rigid timing. In this method, the technique shortens the error correction time for the wiring crowding region, and prevents the timing from deteriorating due to the bypass routing.
However, the local wiring crowding region is enlarged because of increase of a total wiring line amount including wiring lines that require rigid timing due to the high integration and speeding up in the recent LSI. Accordingly, the routing prohibition region for reserving the routing resource generated in the method disclosed in JP2008-227198A is naturally enlarged. When the routing prohibition region is enlarged, an amount of the wiring lines bypassing the routing prohibition region also increases. As the result, the number of routing errors caused by the bypassing routing increases, and accordingly there will be problems that the routing error cannot be eliminated completely and still remains even when the rerouting is carried out after deleting the routing prohibition region for reserving the routing resource and that the correction time of the routing error increases.